The present invention relates to a semiconductor memory device including a capacitor that has a capacitive insulating film of an insulating metal oxide and also relates to a method for fabricating the device.
Recently, as digital technology has been developed, the performance of various electronic units has been further enhanced to catch up with a steep rise in the amount of data to be processed or stored at a time. As a result, semiconductor devices included in a semiconductor chip for those electronic units have been rapidly downsized. Correspondingly, to integrate a dynamic RAM (Random Access Memory) more densely, a technique of using a material with a high dielectric constant (which will be herein referred to as a xe2x80x9chigh-dielectric-constant materialxe2x80x9d), instead of silicon dioxide or silicon nitride widely used, for a capacitive insulating film has been broadly researched and developed. Further, to implement a novel nonvolatile RAM that can operate at a low operating voltage and write and read data at a high speed, a ferroelectric film with spontaneous polarization properties has been vigorously researched and developed.
To realize a highly densely integrated memory with a storage capacity of several megabits using this high-dielectric-constant or ferroelectric material, a stacked memory cell should be used instead of a know planar memory cell.
In this case, the most essential task in fabricating a stacked memory cell is to prevent the interface between a contact plug and the lower electrode of a capacitor from being oxidized during an annealing process performed in an oxygen ambient for crystallizing the high-dielectric-constant or ferroelectric material.
Hereinafter, a known semiconductor memory device will be described with reference to the drawings.
FIG. 6 is a cross-sectional view illustrating a main portion processed in one process step of a first known method for fabricating a semiconductor memory device.
As shown in FIG. 6, a gate electrode 102 is formed over a semiconductor substrate 100 with a gate insulating film 101 interposed therebetween. An insulating sidewall 103 is formed on side faces of the gate electrode 102. A doped layer 104 to be source/drain regions is defined in parts of the semiconductor substrate 100 below the gate electrode 102 to horizontally sandwich the gate electrode 102 therebetween. A transistor, including the gate electrode 102, doped layer 104, and so on, forms part of a semiconductor integrated circuit. And a passivation film 105 is deposited to cover the entire surface of the semiconductor substrate 100 including the semiconductor integrated circuit.
Further, as shown in FIG. 6, a contact hole 106 is formed in the passivation film 105 to reach the doped layer 104. A conductive contact plug 107 is formed in the contact hole 106. The contact plug 107 may be formed in the following manner. First, a conductor layers of polysilicon, tungsten, for example, is deposited over the entire surface of the semiconductor substrate 100 to fill in the contact hole 106. After that, the conductor layer is etched back by a dry etching or CMP (chemical/mechanical polishing) process to remove the excessive parts of the conductor layer outside of the contact hole 106. In this manner, the contact plug 107 can be formed out of the conductor layer in the contact hole 106. In this case, unless the conductor layer and the passivation film 105 are etched at the same rate, it is impossible to make the upper surface of the contact plug 107 flush with that of passivation film 105. However, in this etchback process, the etch rate of the material of the contact plug 107 is usually higher than that of the material of the passivation film 105. Thus, the upper surface of the contact plug 107 will be lower than that of the passivation film 105. As a result, a recess 108 having a wall standing vertically to the upper surface of the contact plug 107 is formed on the contact plug 107.
Furthermore, as shown in FIG. 6, a lower electrode 109 is formed on the passivation film 105, including the recess 108, and connected to the contact plug 107. The lower electrode 109 has a layered structure made up of: Ti layer; oxygen barrier layer of IrO2, Ir, or RuO2; and Pt layer that have been stacked in this order. A capacitive insulating film 110 made of an insulating metal oxide, e.g., high-dielectric-constant or ferroelectric material, is deposited on the lower electrode 109. An upper electrode 111 is formed on the capacitive insulating film 110. A capacitor 112 is made up of the lower electrode 109, capacitive insulating film 110, and upper electrode 111.
However, in the structure shown in FIG. 6, the recess 108 exists on the contact plug 107. In other words, a step 113 has been formed between the upper surfaces of the contact plug 107 and passivation film 105. As a result, the following problems occur. Specifically, if the lower electrode 109 is formed by a sputtering process, for example, on the passivation film 105 including the recess 108, the coverage of the lower electrode 109 will be poor due to the existence of the step 113, i.e., the lower electrode 109 including the oxygen barrier layer partly thins. Thus, the ability of the lower electrode 109 at forming a barrier against oxygen (which will be herein referred to as xe2x80x9coxygen blockabilityxe2x80x9d) deteriorates seriously. Accordingly, if an annealing process is performed in an oxygen ambient to crystallize the high-dielectric-constant or ferroelectric material that will be the capacitive insulating film 110 (which will be herein referred to as xe2x80x9cannealing for crystallizationxe2x80x9d), oxygen reaches the surface of the contact plug 107 by way of the lower electrode 109. As a result, the contact plug 107 is oxidized to cause contact failure. Also, disconnection might also occur because of the partial decrease in thickness of the lower electrode 109.
In view of these problems, a countermeasure process, in which the wall of the recess is formed in a predetermined curved shape after the contact plug has been formed, was proposed in Japanese Laid-Open Publication No. 7-30077.
FIG. 7 is a cross-sectional view illustrating a main portion processed in one process step of a second known method for fabricating a semiconductor memory device as disclosed in Japanese Laid-Open Publication No. 7-30077. In FIG. 7, each member already shown in FIG. 6 is identified by the same reference numeral and the description thereof will be omitted herein.
In the second example, the contact plug 107 is formed as in the first example, and then the passivation film 105 is wet-etched with an etchant including hydrofluoric acid, for example, using a masking pattern (not shown) covering a predetermined region. In this manner, the wall of the recess 108 is formed in a predetermined curved shape as shown in FIG. 7. After that, the capacitor 112 is formed as in the first example.
However, the present inventors found that, it is also impossible in the second example to eliminate the above-mentioned problems completely, i.e., the contact plug 107 is oxidized during the annealing process for crystallizing the capacitive insulating film 110 to cause contact failures. That is to say, the wet etching process adopted for the second example disclosed in Japanese Laid-Open Publication No. 7-33077 is basically isotropic etching. Thus, as shown in FIG. 7, the passivation film 105 is wet-etched isotropically from the upper edge of the contact plug 107 as a start point. As a result, a first steep step 114 is unintentionally formed between the upper surface of the contact plug 107 and portion of the passivation film 105 near the contact plug 107. In addition, the closer to the upper edge of the passivation film 105, the closer to 90 degrees the angle formed by the recess wall with the upper surface of the passivation film 105. Thus, another second steep step 115 is unintentionally formed around the upper edge of the passivation film 105. Accordingly, in the second example, the coverage of the lower electrode 109 is also poor due to the existence of first or second step 114 or 115, and the lower electrode 109 partly thins. Thus, the oxygen blockability of the lower electrode 109 deteriorates. As a result, the contact plug 107 is oxidized during the annealing process for crystallizing the capacitive insulating film 110 to cause contact failures. Disconnection might occur as well because of the partial decrease in thickness of the lower electrode 109.
It is therefore an object of the present invention to prevent the contact plug from being oxidized and thereby eliminate contact failures resulting from the oxidation by suppressing the partial decrease in thickness of the lower electrode due to the existence of the step between the upper surfaces of the contact plug and passivation film.
To achieve this object, an inventive method for fabricating a semiconductor memory device includes the steps of: a) depositing a passivation film over a substrate in which source/drain regions have been defined for a transistor that forms part of a semiconductor integrated circuit; b) forming a contact hole through the passivation film so that the contact hole reaches one of the source/drain regions; c) forming a contact plug in the contact hole so that a recess is left over the contact plug; d) dry-etching the passivation film so that the recess has an expanded opening or a reduced depth; and e) forming a lower electrode connected to the contact plug, a capacitive insulating film of an insulating metal oxide and an upper electrode to make a capacitor. The lower electrode, the capacitive insulating film and the upper electrode are formed in this order on the dry-etched passivation film.
According to the inventive method, a contact plug is formed in a contact hole, which has been formed through a passivation film on a substrate, so that a recess is left over the contact plug. Then, the passivation film is dry-etched so that the opening of the recess is expanded or that the depth of the recess is reduced. Accordingly, it is possible to tilt the wall of the recess less steeply with respect to the upper surface of the contact plug or to reduce the height of a step formed between the upper surfaces of the passivation film and the contact plug (which will be herein referred to as an xe2x80x9con-plug stepxe2x80x9d). Thus, when a lower electrode for a capacitor is formed on the passivation film so as to be connected to the contact plug, it is possible to prevent the lower electrode from partially thinning. Consequently, if the lower electrode includes an oxygen barrier layer, the oxygen blockability of the lower electrode improves. Accordingly, even if an annealing process is performed in an oxygen ambient to crystalline an insulating metal oxide (i.e., a high-dielectric-constant or ferroelectric material) for a capacitive insulating film, no oxygen diffuses toward and reaches the contact plug by way of the lower electrode. As a result, the contact plug is not oxidized, and no contact failures will occur.
In one embodiment of the present invention, the step d) may be performed using an Ar gas.
Then, a physical etching can be performed by controlling the direction in which Ar ions are implanted. Thus, only those portions of the passivation film near the recess can be etched as intended. Accordingly, the wall of the recess can have a desired tilt angle or desired depth. In other words, the recess can be formed in a desired shape. Thus, it is possible to suppress the partial decrease in thickness of the lower electrode due to the existence of the on-plug step. As a result, the oxygen blockability of the lower electrode, including the oxygen barrier layer, should improve as intended.
In another embodiment, the step d) may be performed with the substrate heated to a temperature between 100xc2x0 C. and 700xc2x0 C., both inclusive.
Then, the recess can be formed in a desired shape. Thus, it is possible to suppress the partial decrease in thickness of the lower electrode due to the existence of the on-plug step. As a result, the oxygen blockability of the lower electrode, including the oxygen barrier layer, should improve as intended.
In still another embodiment, the step d) may include setting a tilt angle, formed by a wall of the recess with the upper surface of the contact plug, at 70 degrees or less.
Then, it is possible to suppress the partial decrease in thickness of the lower electrode due to the existence of the on-plug step. As a result, the oxygen blockability of the lower electrode, including the oxygen barrier layer, should improve as intended.
In yet another embodiment, the step d) may include setting the depth of the recess at 50 nm or less.
Then, it is possible to suppress the partial decrease in thickness of the lower electrode due to the existence of the on-plug step. As a result, the oxygen blockability of the lower electrode, including the oxygen barrier layer, should improve as intended.
A first inventive semiconductor memory device includes: a passivation film formed over a substrate in which source/drain regions have been defined for a transistor that forms part of a semiconductor integrated circuit; a contact hole, which has been formed through the passivation film to reach one of the source/drain regions; a contact plug, which has been formed in the contact hole so that a recess is left over the contact plug; a lower electrode for a capacitor, the lower electrode having been formed on the passivation film and connected to the contact plug; a capacitive insulating film formed on the lower electrode out of an insulating metal oxide; and an upper electrode for the capacitor, the upper electrode having been formed on the capacitive insulating film. In this device, a tilt angle formed by a wall of the recess with the upper surface of the contact plug is 70 degrees or less.
In the first inventive device, a contact plug is formed in a contact hole, which has been formed through a passivation film on a substrate, so that a recess is left over the contact plug. And a tilt angle formed by the wall of the recess with the upper surface of the contact plug is 70 degrees or less. Thus, when a lower electrode for a capacitor is formed on the passivation film so as to be connected to the contact plug, it is possible to prevent the lower electrode from partially thinning due to the existence of an on-plug step. Consequently, if the lower electrode includes an oxygen barrier layer, the oxygen blockability of the lower electrode improves. Accordingly, even if an annealing process is performed in an oxygen ambient to crystalline a high-dielectric-constant or ferroelectric material for a capacitive insulating film, no oxygen diffuses toward and reaches the contact plug by way of the lower electrode. As a result, the contact plug is not oxidized, and no contact failures will occur.
A second inventive semiconductor memory device includes: a passivation film formed over a substrate in which source/drain regions have been defined for a transistor that forms part of a semiconductor integrated circuit; a contact hole, which has been formed through the passivation film to reach one of the source/drain regions; a contact plug, which has been formed in the contact hole so that a recess is left over the contact plug; a lower electrode for a capacitor, the lower electrode having been formed on the passivation film and connected to the contact plug; a capacitive insulating film formed on the lower electrode out of an insulating metal oxide; and an upper electrode for the capacitor, the upper electrode having been formed on the capacitive insulating film. In this device, the recess has a depth of 50 nm or less.
In the second inventive device, a contact plug is formed in a contact hole, which has been formed through a passivation film on a substrate, so that a recess is left over the contact plug. And the recess has a depth of 50 nm or less. Thus, when a lower electrode for a capacitor is formed on the passivation film so as to be connected to the contact plug, it is possible to prevent the lower electrode from partially thinning due to the existence of an on-plug step. Consequently, if the lower electrode includes an oxygen barrier layer, the oxygen blockability of the lower electrode improves. Accordingly, even if an annealing process is performed in an oxygen ambient to crystalline a high-dielectric-constant or ferroelectric material for a capacitive insulating film, no oxygen diffuses toward and reaches the contact plug by way of the lower electrode. As a result, the contact plug is not oxidized, and no contact failures will occur.